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16951B Datasheet(PDF) 10 Page - Agilent(Hewlett-Packard)

Part # 16951B
Description  Logic Analyzer
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

16951B Datasheet(HTML) 10 Page - Agilent(Hewlett-Packard)

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Agilent 16910A and 16911A Specifications and Characteristics
Timing (Asynchronous) Analysis Mode
Conventional Timing
Transitional Timing [8]
Sample rate on all channels
500 MHz
500 MHz
Sample rate in half channel mode
1000 MHz
N/A
Number of channels
16910A: 102 x (number of modules)
16910A: For sample rates < 500 MHz:
102 x (number of modules)
For 500 MHz sample rate:
102 x (number of modules) – 34
16911A: 68 x (number of modules)
16911A: For sample rates < 500 MHz:
68 x (number of modules)
For 500 MHz sample rate:
68 x (number of modules) – 34
Maximum channels on a single time
16910A: 510
16910A: 510
base and trigger
16911A: 340
16911A: 340
Number of independent analyzers [5]
2
2
Sample period (half channel)
1.0 ns
N/A
Minimum sample period (full channel)
2.0 ns
2.0 ns
Minimum data pulse width
1 sample period + 1.0 ns
1 sample period + 1.0 ns
Time interval accuracy
± (1 sample period + 1.25 ns + 0.01% of
± (1 sample period + 1.25 ns + 0.01% of
time interval reading)
time interval reading)
Memory depth in full channel mode
Option 256: 256 K samples
Option 256: 256 K samples
(Option 256 is included in base price)
Option 001: 1 M samples
Option 001: 1 M samples
Option 004: 4 M samples
Option 004: 4 M samples
Option 016: 16 M samples
Option 016: 16 M samples
Option 032: 32 M samples
Option 032: 32 M samples
Memory depth in half channel mode
Option 256: 512 K samples
N/A
(Option 256 is included in base price)
Option 001: 2 M samples
Option 004: 8 M samples
Option 016: 32 M samples
Option 032: 64 M samples
Maximum trigger sequence speed
250 MHz
250 MHz
Maximum trigger sequence levels
16
16
[5] Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
[8] Transitional timing speed and memory depth are halved unless a spare pod pair (34 channels) is unassigned.


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