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ST7585 Datasheet(PDF) 9 Page - Sitronix Technology Co., Ltd.

Part # ST7585
Description  66 x 102 Dot Matrix LCD Controller/Driver
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Manufacturer  SITRONIX [Sitronix Technology Co., Ltd.]
Direct Link  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST7585 Datasheet(HTML) 9 Page - Sitronix Technology Co., Ltd.

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ST7585
Ver 1.0c
9/51
2009/04/14
Pin Name
Type
Description
No. of Pins
ERD
I
Read/Write execution control pin. When parallel interface is selected:
MPU Type
ERD
Description
6800 series
E
Read/Write control input pin.
R/W=
”H“: When E is “H”, D[7:0] are in an
output status.
R/W=
”L“: Signals on D[7:0] are latched at
the falling edge of E signal.
8080 series
/RD
Read enable input pin.
When /RD is
“L”, D[7:0] are in output status.
ERD is not used in serial interfaces and should fix to
“H” by VDD1.
1
I/O
When using 8-bit parallel interface: 6800 or 8080 mode
8-bit bi-directional data bus. Connect to the data bus of 8-bit microprocessor.
When CSB is non-active (CSB=
“H”), D[7:0] pins are high impedance.
I
When using serial interface: 4-LINE or 3-LINE
D7=SCLK : Serial clock input.
D6=SDA : Serial data input.
D5=A0 : Command / Data selection (unused in 3-Line SPI; fix to H by VDD1).
D4=CSB : Chip select pin.
D[3:0] : Not used and should fix to
“H” by VDD1.
D[7:0]
I, O
When using I
2C interface
D7=SCLK : Serial clock input.
D6=SDA_IN
*1 : Serial data input.
D[5:3] : SDA_OUT
*1 : Outputs for acknowledge-bit of the I2C protocol.
D[2]= Not used and should fix to
“H” by VDD1.
D[1:0]=SA[1:0] : Slave address bits. Must set to
“H” by VDD1 or “L” by VSS1.
D[6:3] must connect together (SDA).
*1
CSB is not used in I
2C interface and should fix to “H” by VDD1.
8
Note:
1.
By connecting SDA_IN and SDA_OUT externally, the SDA line becomes fully I
2C interface compatible. Separating
acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG applications,
the ITO resistance and the pull-up resistor will form a voltage divider which affects acknowledge-signal level. Larger
ITO resistance will raise the acknowledge-signal level and system cannot recognize this level as a valid logic
“0” level.
By separating SDA_IN from SDA_OUT, the IC can be used in a mode which ignores the acknowledge-bit. For
applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace to
guarantee a valid low level.
2.
After VDD1 is turned ON, any MPU interface pins cannot be left floating.


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