0.1

μF

2.048V

DGND

AGND

COM

CS

SCLK

DIN

DOUT

SSTRB

SHDN

+2.5V

N.C.

0.01

μF

CH7

VREF

C1

0.1

μF

0V TO

2.048V

ANALOG

INPUT

OSCILLOSCOPE

CH1

CH2

CH3

CH4

* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)

MAX1245

+2.5V

1.5MHz

OSCILLATOR

SCLK

SSTRB

DOUT*

Figure 5. Quick-Look Circuit

that source impedances below 1k

Ω do not significantly

affect the AC performance of the ADC. Higher source

impedances can be used if an input capacitor is con-

nected to the analog inputs, as shown in Figure 5. Note

that the input capacitor forms an RC filter with the input

source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 2.25MHz

small-signal bandwidth, so it is possible to digitize

high-speed transient events and measure periodic sig-

nals with bandwidths exceeding the ADC’s sampling

rate by using undersampling techniques. To avoid

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog

age. However, for accurate conversions near full scale,

be lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the sup-

plies, do not forward bias the protection diodes of

off channels over two milliamperes, as excessive

current will degrade the conversion accuracy of the

on channel.

Quick Look

To quickly evaluate the MAX1245’s analog perfor-

mance, use the circuit of Figure 5. The MAX1245

requires a control byte to be written to DIN before each

$FF (HEX), which trigger single-ended unipolar conver-

sions on CH7 in external clock mode without powering

down between conversions. In external clock mode, the

SSTRB output pulses high for one clock period before

the most significant bit of the 12-bit conversion result is

shifted out of DOUT. Varying the analog input to CH7

alters the sequence of bits from DOUT. A total of 15

clock cycles is required per conversion. All transitions

of the SSTRB and DOUT outputs occur on the falling

edge of SCLK.

How to Start a Conversion

A conversion is started by clocking a control byte into

DIN. With CS low, each rising edge on SCLK clocks a

bit from DIN into the MAX1245’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

MSB of the control byte. Until this first “start” bit arrives,

any number of logic “0” bits can be clocked into DIN

with no effect. Table 1 shows the control-byte format.

The MAX1245 is compatible with Microwire, SPI, and

QSPI devices. For SPI, select the correct clock polarity

and sampling edge in the SPI control registers: set

CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all

transmit a byte and receive a byte at the same time.

Using the

Typical Operating Circuit, the simplest soft-

ware interface requires only three 8-bit transfers to

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

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