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MAX16814ATP+ Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX16814ATP+ Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 25 page Integrated, 4-Channel, High-Brightness LED Driver with High-Voltage DC-DC Controller _______________________________________________________________________________________ 9 Pin Description (continued) PIN NAME FUNCTION TQFN TSSOP 12 15 OUT2 LED String Cathode Connection 2. OUT2 is the open-drain output of the linear current sink that controls the current through the LED string connected to OUT2. OUT2 sinks up to 150mA. If unused, connect OUT2 to LEDGND. 13 16 LEDGND LED Ground. LEDGND is the return path connection for the linear current sinks. Connect SGND, LEDGND, and PGND at a single point. 14 17 OUT3 LED String Cathode Connection 3. OUT3 is the open-drain output of the linear current sink that controls the current through the LED string connected to OUT3. OUT3 sinks up to 150mA. If unused, connect OUT3 to LEDGND. 15 18 OUT4 LED String Cathode Connection 4. OUT4 is the open-drain output of the linear current sink that controls the current through the LED string connected to OUT4. OUT4 sinks up to 150mA. If unused, connect OUT4 to LEDGND. 16 19 CS Current-Sense Input. CS is the current-sense input for the switching regulator. A sense resistor connected from the source of the external power MOSFET to PGND sets the switching current limit. A resistor connected between the source of the power MOSFET and CS sets the slope compensation ramp rate (see the Slope Compensation section). 17 20 PGND Power Ground. PGND is the switching current return path connection. Connect SGND, LEDGND, and PGND at a single point. 18 1 NDRV Switching n-MOSFET Gate-Driver Output. Connect NDRV to the gate of the external switching power MOSFET. 19 2 DRV MOSFET Gate-Driver Supply Input. Connect a resistor between VCC and DRV to power the MOSFET driver with the internal 5V regulator. Bypass DRV to PGND with a minimum of 0.1µF ceramic capacitor. 20 3 VCC 5V Regulator Output. Bypass VCC to SGND with a minimum of 1µF ceramic capacitor as close as possible to the device. — — EP Exposed Pad. Connect EP to a large-area contiguous copper ground plane for effective power dissipation. Do not use as the main IC ground connection. EP must be connected to SGND. |
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