FB

1

2

3

4

TZE

PCL

OTM

VDD

GND

DRN

VCG

8

7

6

5

TPS92210

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SLUS989 – JANUARY 2010

PIN CONFIGURATION

PIN DESCRIPTIONS

TERMINAL

I/O

DESCRIPTION

NAME

No.

The DRN pin is the drain of the internal low voltage power MOSFET of the TPS92210 and carries the peak primary

DRN

6

O

between DRN and VDD is used to provide initial bias at startup.

mode of TPS92210. For peak-current mode control, this pin is connected to the emitter of the feedback opto

FB

1

I

coupler. In constant on-time control, the minimum switching period is programmed by forcing a constant current into

this pin.

This GND pin is the current return terminal for both the analog and power signals in the TPS92210. This terminal

GND

7

—

the OTM pin is internally regulated at 3 V and used to program the on-time of the cascode (flyback) switch by

OTM

4

I

to this pin for constant-on time control. The range of impedance connected at this pin determines the system fault

response (latch-off or shutdown/retry) to overload and brownout fault conditions. An external shutdown/retry

response can be initiated by pulling this pin low below 1 V.

The PCL pin programs the peak primary inductor current that is reached each switching cycle. The primary current

PCL

3

I

power resistor from this pin to the quiet return of GND.

A resistive divider between the primary-side auxiliary winding and this pin is used to detect when the transformer is

TZE

2

I

demagnetized resulting in transformer zero energy. The ratio of the resistive divider at this pin can also be used to

program the output overvoltage protection (OVP) feature.

The VCG pin provides the bias voltage for the gate of the cascode MOSFET. Place a 0.1-µF ceramic capacitor

VCG

5

—

between VCG and GND, as close as possible to the high-voltage MOSFET. This pin also provides start-up bias

VDD is the bias supply pin for the TPS92210. It can be derived from an external source, or an auxiliary winding.

VDD

8

—

Place a 0.1-µF ceramic capacitor between VDD and GND, as close to the device as possible. This pin also enables

and disables the general functions of the TPS92210 using the UVLO feature.

Copyright © 2010, Texas Instruments Incorporated

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Product Folder Link(s): TPS92210