AD9269BCPZ-40 datasheet(29/40 Pages) AD

Part #	AD9269BCPZ-40

Description	16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

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AD9269

Rev. 0 | Page 29 of 40

SERIAL PORT INTERFACE (SPI)

The AD9269 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a struc-

tured register space provided inside the ADC. The SPI provides

added flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

can be further divided into fields, which are documented in the

Memory Map section. For detailed operational information, see

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK, the SDIO, and

the CSB (see Table 14). The SCLK (a serial clock) is used to syn-

chronize the read and write data presented from and to the ADC.

The SDIO (serial data input/output) is a dual-purpose pin that

allows data to be sent to and read from the internal ADC

memory map registers. The CSB (chip select bar) is an active-

low control that enables or disables the read and write cycles.

Table 14. Serial Port Interface Pins

Function

SCLK

Serial clock. A serial shift clock input that is used to

synchronize serial interface reads and writes.

SDIO

Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

CSB

Chip select bar. An active-low control that gates the read

and write cycles.

The falling edge of the CSB, in conjunction with the rising edge

of SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 59 and

Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, permanently enabling the device; this is

called streaming. The CSB can stall high between bytes to allow

for additional external timing. When the CSB is tied high, the

SPI functions are placed in high impedance mode. This mode

turns on any secondary functions of the SPI function pins.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and the length of the data

stream is determined by the W1 and W0 bits, as shown in

Figure 59.

All data is composed of 8-bit words. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read com-

mand or a write command is issued. This allows the serial data

input/output (SDIO) pin to change direction from an input to

an output at the appropriate point in the serial frame.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

Data can be sent in MSB-first mode or in LSB-first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Table 14 constitute the physical interface

between the programming device of the user and the serial port

of the AD9269. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

DON’T CARE

SDIO

SCLK

CSB

tS

tDH

tCLK

tDS

tH

tHIGH

tLOW

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

Figure 59. Serial Port Interface Timing Diagram

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AD9269BCPZ-40 Datasheet(PDF) 29 Page - Analog Devices

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