AD9269BCPZ-20 datasheet(35/40 Pages) AD

Part #	AD9269BCPZ-20

Description	16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

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Manufacturer	AD [Analog Devices]

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AD9269

Rev. 0 | Page 35 of 40

Bit 1—Open

Bit 0—Disable SDIO Pull-Down

This bit can be set high to disable the internal 30 kΩ pull-down

on the SDIO pin, which can be used to limit the loading when

many devices are connected to the SPI bus.

QEC Control 0 (Register 0x110)

Bits[7:6]—Open

Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain

These bits can be used to freeze the corresponding dc, phase,

and gain offset corrections of the quadrature error correction

(QEC) independently. When asserted high, QEC is applied

using frozen values, and the estimation of the quadrature errors

is halted.

Bits[2:0]—DC Enable/Phase Enable/Gain Enable

These bits allow the corresponding dc, phase, and gain offset

corrections to be enabled independently.

QEC Control 1 (Register 0x111)

Bits[7:3]—Open

Bit 2—Force DC

When set high, this bit forces the initial static correction values

from Register 0x11A and Register 0x11B for the I data and

Register 0x11C and Register 0x11D for the Q data.

Bit 1—Force Phase

When set high, this bit forces the initial static correction values

from Register 0x118 and Register 0x119.

Bit 0—Force Gain

When set high, this bit forces the initial static correction values

from Register 0x116 and Register 0x117.

QEC Gain Bandwidth Control (Register 0x112)

Bits[7:5]—Open

Bits[4:0]—KEXP_GAIN

These bits adjust the time constants of the gain control feedback

loop for quadrature error correction.

QEC Phase Bandwidth Control (Register 0x113)

Bits[7:5]—Open

Bits[4:0]—KEXP_PHASE

These bits adjust the time constants of the phase control

feedback loop for quadrature error correction.

QEC DC Bandwidth Control (Register 0x114)

Bits[7:5]—Open

Bits[4:0]—KEXP_DC

These bits adjust the time constants of the dc control feedback

loop for quadrature error correction.

QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and

Register 0x117)

Bits[14:0]—Initial Gain

When the force gain bit (Register 0x111, Bit 0) is set high, these

values are used for gain error correction.

QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and

Register 0x119)

Bits[12:0]—Initial Phase

When the force phase bit (Register 0x111, Bit 1) is set high,

these values are used for phase error correction.

QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and

Register 0x11B)

Bits[13:0]—Initial DC I

When the force dc bit (Register 0x111, Bit 2) is set high, these

values are used for dc error correction.

QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and

Register 0x11D)

Bits[13:0]—Initial DC Q

When the force dc bit (Register 0x111, Bit 2) is set high, these

values are used for dc error correction.

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AD9269BCPZ-20 Datasheet(PDF) 35 Page - Analog Devices

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