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MAX6366HKA__-T Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX6366HKA__-T Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 15 page SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable Gating _______________________________________________________________________________________ 9 OUT goes high and stays high regardless of any sub- sequent transitions on CE IN during the reset event. When CE OUT is disconnected from CE IN, CE OUT is actively pulled up to OUT. The propagation delay through the chip-enable circuit- ry depends on both the source impedance of the drive to CE IN and the capacitive loading at CE OUT. The chip-enable propagation delay is production tested from the 50% point of CE IN to the 50% point of CE OUT, using a 50 Ω driver and 50pF load capacitance. Minimize the capacitive load at CE OUT to minimize propagation delay, and use a low-output-impedance driver. Backup-Battery Switchover In a brownout or power failure, it may be necessary to preserve the contents of the RAM. With a backup bat- tery installed at BATT, the MAX6365–MAX6368 auto- matically switch the RAM to backup power when VCC falls. The MAX6367 has a BATT ON output that goes high in battery-backup mode. These devices require two conditions before switching to battery-backup mode: 1) VCC must be below the reset threshold. 2) VCC must be below VBATT. Table 1 lists the status of the inputs and outputs in bat- tery-backup mode. The devices do not power up if the only voltage source is on BATT. OUT only powers up from VCC at startup. Manual Reset Input (MAX6365 Only) Many µP-based products require manual reset capabili- ty, allowing the user or external logic circuitry to initiate a reset. For the MAX6365, a logic low on MR asserts reset. Reset remains asserted while MR is low and for a mini- mum of 150ms (tRP) after it returns high. MR has an inter- nal 20k Ω pullup resistor to VCC. This input can be driven with TTL/CMOS logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; exter- nal debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environ- ment, connect a 0.1µF capacitor from MR to GND to pro- vide additional noise immunity. Figure 1. Reset and Chip-Enable Timing VCC OR BATT RESET THRESHOLD VTH RESET CE IN CE OUT RESET * tRD tRD tRP tRP IF CE IN GOES HIGH BEFORE RESET ASSERTS, CE OUT GOES HIGH WITHOUT DELAY AS CE IN GOES HIGH. RESET-TO-CE OUT DELAY (12 μs) * PIN STATUS VCC Disconnected from OUT OUT Connected to BATT BATT Connected to OUT. Current drawn from the battery is less than 1 μA (at VBATT = 2.8V, excluding IOUT) when VCC = 0. RESET/RESET Asserted BATT ON High state MR, RESET IN, CE IN, WDI Inputs ignored CE OUT Connected to OUT Table 1. Input and Output Status in Battery-Backup Mode |
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