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SKY73126-31 Datasheet(PDF) 6 Page - Skyworks Solutions Inc.

Part # SKY73126-31
Description  161.92 MHz High Performance VCO/Synthesizer
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Manufacturer  SKYWORKS [Skyworks Solutions Inc.]
Direct Link  http://www.skyworksinc.com
Logo SKYWORKS - Skyworks Solutions Inc.

SKY73126-31 Datasheet(HTML) 6 Page - Skyworks Solutions Inc.

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DATA SHEET • SKY73126-31 VCO/SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
6
February 24, 2010 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201112C
Table 6. Word 2: DPLL Control Hold Register
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
Default Value
(Binary)
wd_3, wd_2, wd_1,
wd_0
Address bits [3:0]. Must be set to
0010b (see Table 3).
0010
0010
dpll_ctrl
DPLL control [21:4]
Reserved
00000000000
0000000
test_mux
Lock detect and diagnostic output
select [24:22]
Note: Logic output is via LD signal
(pin 12)
Bits [24:22]:
0 0 0 = lock detect output or vendor ID read-back
0 0 1 = R-divider output
0 1 0 = N-divider output
0 1 1 = capacitor overflow
1 0 0 = capacitor underflow
1 0 1 = VCO high comparator
1 1 0 = VCO low comparator
1 1 1 = DPLL test
Note: When test_mux = 000, the vendor ID is output to
pin 12 if vendor ID read-back has been initialized.
Otherwise, when test_mux = 000, pin 12 outputs the
lock detect signal.
000
000
sd_sel
Internal operating voltage control bit
for the synthesizer [25]
Note: this bit needs to be programmed
together with Word 1, bit [11], and
Word 1, bit [12].
See nr_sel parameter (Word 1, bit [11])
0
0
rsvd
Reserved [31:26]
Reserved
000000
000000
Table 7. Word 3: Frequency Control Hold Register (1 of 2)
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
Default Value
(Binary)
wd_3, wd_2, wd_1,
wd_0
Address bits [3:0]. Must be set to
0011b (see Table 3).
0011
0011
dpll_en
VCO auto tuning enable flag [4]
Bit [4]:
0 = disable VCO auto tuning
1 = enable VCO auto tuning
Refer to Figure 7
0
ndiv
N-divider/prescaler mode for control
of M and A counters [20:5]
Bits [20:5]:
For 8/9 prescaler mode:
bits [7:5]
= A-counter bits [2:0] (bit [3] = 0)
bits [19:8] = M-counter bits [11:0]
bit [20]
= 0
For 16/17 prescaler mode:
bits [8:5]
= A-counter bits [3:0]
bits [20:9] = M-counter bits [11:0]
Application
dependent
00000000000
00000


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