DATA SHEET • SKY73126-31 VCO/SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

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February 24, 2010 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201112C

Vtune

R1

SP1

SC1

N

PS

CPO RF

R1

Divider

RF

PFD

Mux

(LD/Test)

RF Charge

Pump

N

Divider

Varactor

VCO

S1315

P/P+1

Prescaler

/4

Divider

RF_OUT

PLL

Loop Filter

3-Wire

Serial

Interface

TCXO_IN

(10 or 32 MHz)

CLK

LE

3.3 V

Voltage

Regulator

VCC (5 V)

DATA

LD

Figure 2. SKY73126-31 Functional Block Diagram

Table 1. SKY73126-31 Signal Descriptions

Pin #

Name

Description

Pin #

Name

Description

1

VCC

+5 V DC power supply

9

GND

Ground

2

GND

Ground

10

DATA

Serial port SPI data input (master out slave in)

3

RF_OUT

RF output

11

LE

Serial port latch enable

4

GND

Ground

12

LD

Lock detect output

5

N/C

No connection

13

GND

Ground

6

GND

Ground

14

TCXO_IN

Frequency reference input

7

N/C

No connection

15

GND

Ground

8

CLK

Serial port clock

16

GND

Ground

Technical Description

The SKY73126-31 is a BiCMOS integer-N synthesizer that offers

high performance, low cost, and low power consumption. The

device also provides programmable charge pump gain.

Serial I/O Control Interface

The SKY73126-31 is programmed through a three-wire serial bus

control interface. The three-wire interface consists of three

signals: CLK (pin 8), LE (pin 11), and the bit serial data line DATA

(pin 10). A serial data input timing diagram is shown in Figure 3.

Timing parameter values are provided in Table 2.

Figure 4 depicts the serial bus, which consists of one 32-bit load

register and four separate 28-bit hold registers. Data is initially

clocked into the load register starting with the Most Significant Bit

(MSB) and ending with the Least Significant Bit (LSB).

The LE signal is used to gate the clock to the load register,

requiring the LE signal to be brought low before the data load.

Data is shifted on the rising edge of CLK. The falling edge of LE

latches the data into the appropriate hold register from the load

register. This programming sequence must be repeated to fill all

four hold registers.

The specific hold register addresses are determined by the wd_0,

wd_1, wd_2, and wd_3 parameters in the load register. These

are the four LSBs (bits [3:0]) as shown in Figure 4. Table 3 lists

the four hold registers and their respective addresses as

determined in the load register.