Functional description

SCLT3-8BT8

8/33

Doc ID 15191 Rev 3

Figure 5.

Low side front-end input topology including the ESD surge protection

and the LED driver

2.3

The input digital filter

A digital filter is implemented between the input state comparator and the input state

register. It consists of a 2-step sampling circuit that is controlled by an oscillator as shown on

Figure 6.

This period can be adjusted between 20 µs and 3000 µs and is compatible with the

IEC 61131-2 standard as shown on Table 2.

Being placed in the front end of the module, this filter increases the transient immunity of the

SCLT and its SPI logic circuitry. It also simplifies the input management software task of the

ASIC controller.

V

R

IN

LD

COM

P

V

R

IN

LD

COM

P

Filter

Table 2.

Typical setting of the digital filter timings

Input speed

Fast

Medium

Slow

Input frequency

60 kHz

20 kHz

5 kHz

300 Hz

20 µs

50 µs

230 µs

3.0 ms

OSC resistance

51 k

Ω

150 k

Ω

82 k

Ω

1.3 M

Ω

10 µs

25 µs

115 µs

1500 µs

DVR connection

Divider ratio

8

8

64

64