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SCLT3-8BT8-TR Datasheet(PDF) 9 Page - STMicroelectronics

Part # SCLT3-8BT8-TR
Description  Protected digital input termination with serialized state transfer
Download  33 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SCLT3-8BT8-TR Datasheet(HTML) 9 Page - STMicroelectronics

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SCLT3-8BT8
Functional description
Doc ID 15191 Rev 3
9/33
Figure 6.
Two-step digital filter placed after the analog section of the logic input
2.4
Operation of the SCLT with the SPI bus
The SPI bus master controller manages the data transfer with the chip select signal /CS and
controls the data shift in the register with the clock SCK signal. This data transfer operation
is defined by the phase CPHA and the polarity CPOL of the clock. The SCLT runs with an SPI
master protocol mode: CPHA = 0 and CPOL = 0.
Figure 7.
Serial data format frame with a master running in CPHA = 0 and CPOL = 0
mode
The transfer of the SCLT input state in the SPI register starts when the chip select signal
/CS falls and ends when this chip select signal rises back.
The transfer of data out of the SCLT slave MISO output starts immediately when the chip
select signal /CS goes low. The input MOSI is captured and presented to the shift register
on each rising edge of the clock SCK. The data are shifted in this register on each falling
edge of the serial clock SCK, the data bits are written on the output MISO with the most
significant bit first.
During all operations, VDD is held stable within the specified operating range.
DQ
/Q
CK
DQ
/Q
CK
Q
S
R
CKF
IN
OUT
DQ
/Q
CK
DQ
/Q
CK
DQ
/Q
CK
DQ
/Q
CK
DQ
/Q
CK
Q
S
R
Q
S
R
S
R
CKF
IN
OUT
DQ
/Q
CK
DQ
/Q
CK
CKF
IN
OUT
CKF
IN
OUT
MISO
MOSI
SCK
CS
DATA CAPTURE
MSB
M
14
13
12
MSB
S
14
13
12
12
3
4
1234
3
2
1
LSB
M
3
2
1
LSB
S
MSB
M
MSB
S
13
14
15
16
13
14
15
16
MISO
MOSI
SCK
CS
DATA CAPTURE
MSB
M
14
13
12
MSB
S
14
13
12
12
3
4
1234
3
2
1
LSB
M
3
2
1
LSB
S
MSB
M
MSB
S
13
14
15
16
13
14
15
16


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