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UCD9224 Datasheet(PDF) 11 Page - Texas Instruments |
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UCD9224 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 34 page UCD9224 www.ti.com SLVSA35 – JANUARY 2010 PIN DESCRIPTIONS PIN NO. PIN NAME DESCRIPTION 1 CS-3A Power stage 3A current sense input and input to analog comparator 4 2 CS-1B Power stage 1B current sense input 3 CS-2A Power stage 2A current sense input and input to analog comparator 2 4 Vin/Iin Input supply sense, alternates between Vin and Iin 5 nRESET Active low device reset input, pullup to 3.3V with 10k Ω resistor 6 FLT-1A External fault input 1A, active high 7 FLT-1B External fault input 1B, active high 8 FLT-2A External fault input 2A, active high 9 SRE-1A Synchronous rectifier enable output 1A, active high 10 PMBus_Clock PMBus Clock, pullup to 3.3V with 2k Ω resistor 11 PMBus_Data PMBus Data, pullup to 3.3V with 2k Ω resistor 12 DPWM-1A Digital Pulse Width Modulator output 1A 13 DPWM-1B Digital Pulse Width Modulator output 1B 14 DPWM-2A Digital Pulse Width Modulator output 2A 15 SRE-2A Synchronous rectifier enable output 2A, active high 16 DPWM-3A Digital Pulse Width Modulator output 3A 17 SRE-3A Synchronous rectifier enable output 3A, active high 18 SRE-1B Synchronous rectifier enable output 1B, active high 19 PMBus_Alert PMBus Alert, pullup to 3.3V with 2k Ω resistor 20 PMBus_Cntl PMBus Control, pullup to 3.3V with 2k Ω resistor 21 SEQ-1 Sequencing Input/Output 22 SEQ-2 Sequencing Input/Output 23 TMUX-0 Temperature multiplexer select output S0, Vin/Iin select 24 TMUX-1 Temperature multiplexer select output S1 25 FLT-3A External fault input 3A, active high 26 PGood Power Good indication, Active high open-drain output. Pull-up to 3.3V with 10k Ω resistor. 27 TCK JTAG Test clock 28 TDO / Sync_Out JTAG Test data out (muxed with Sync_Out for synchronizing switching frequency across devices) 29 TDI / Sync_In JTAG Test data in (muxed with Sync_In for synchronizing switching frequency across devices) tie to V33D with 10kOhm resistor 30 TMS JTAG Test mode select – tie to V33D with 10k Ω resistor 31 nTRST JTAG Test reset – tie to ground with 10k Ω resistor 32 DGND1 Digital ground 33 V33D Digital core 3.3V supply 34 V33A Analog 3.3V supply 35 BPCap 1.8V bypass capacitor connection 36 AGND1 Analog ground 37 EAP1 Error analog, differential voltage. Positive channel #1 input 38 EAN1 Error analog, differential voltage. Negative channel #1 input 39 EAP2 Error analog, differential voltage. Positive channel #2 input 40 EAN2 Error analog, differential voltage. Negative channel #2 input 41 V33FB Connection to the base of the 3.3V linear regulator transistor. (no connect if not using an external transistor) 42 CS-1A Power stage 1A current sense input and input to analog comparator 1 43 ADDR-1 Address sense input. Channel 1 44 ADDR-0 Address sense input. Channel 0 45 Vtrack Voltage track input Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11 |
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