TPS657052

TPS657051

SLVSA08 – FEBRUARY 2010

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

SIZE FOR WCSP

PACKAGE

PACKAGE

OPTIONS

I2C

PACKAGE

VERSION

CODE

MARKING

DCDC1 3.3V FIX, DCDC2 1.8 V

D = 2076 µm ± 25 µm

FIX

–40°C to 85°C

TPS657051

YZH

N/A

WCSP

TPS657051

E = 2076 µm ± 25 µm

DCDC CONVERTERS 400mA,

LDO VOUT 3.0V FIX, 200mA

DCDC1 3.3V FIX, DCDC2 1.8 V

D = 2076 µm ± 25 µm

FIX

–40°C to 85°C

TPS657052

YZH

N/A

WCSP

TPS657052

E = 2076 µm ± 25 µm

DCDC CONVERTERS 400mA,

LDO VOUT 2.8V FIX, 200mA

(1)

NO NOTE FOR PART NO IN SOURCE? FC

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VALUE / UNIT

Input voltage range on all pins except A/PGND pins with respect to AGND

–0.3 to 7 V

Voltage range on pin VLDO1 with respect to AGND

–0.3 to 3.6 V

Current at L1, VLDO1, VINLDO1, PGND

600 mA

Current at AGND

20 mA

Current at all other pins

3 mA

Continuous total power dissipation

See Dissipation Rating Table

–40°C to 85°C

125°C

–65°C to 150°C

DISSIPATION RATINGS

DERATING FACTOR

DEVICE

PACKAGE

POWER RATI4NG

POWER RATING

POWER RATING

YZH

185

540mW

5.4mW

297mW

216mW

YZH

75

1.3W

13.3mW

0.7W

0.5W

(1)

The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.

(2)

The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground.

2

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