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74ABT821PW Datasheet(PDF) 9 Page - NXP Semiconductors |
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74ABT821PW Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74ABT821_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 February 2010 9 of 16 NXP Semiconductors 74ABT821 10-bit D-type flip-flop; positive-edge trigger; 3-state a. Input pulse definition b. Test circuit Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Test circuit for measuring switching times 001aai298 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
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