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HMT164U6AFR6C-G8 Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HMT164U6AFR6C-G8 Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 57 page Rev. 0.1 / Dec 2008 7 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2. Pin Architecture 2.1 Pin Definition Pin Name Description Pin Name Description A0–A13 SDRAM address bus SCL I2C serial bus clock for EEPROM BA0–BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM RAS SDRAM row address strobe SA0–SA2 I2C slave address select for EEPROM CAS SDRAM column address strobe VDD* SDRAM core power supply WE SDRAM write enable VDDQ* SDRAM I/O Driver power supply S0–S1 DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply CKE0–CKE1 SDRAM clock enable lines VREFCA SDRAM command/address reference supply ODT0–ODT1 On-die termination control lines VSS Power supply return (ground) DQ0–DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CB0–CB7 DIMM ECC check bits NC Spare pins (no connect) DQS0–DQS8 SDRAM data strobes (positive line of differential pair) TEST Memory bus analysis tools (unused on memory DIMMS) DQS0–DQS8 SDRAM data strobes (negative line of differential pair) RESET Set DRAMs to Known State DM0–DM8 SDRAM data masks/high data strobes (x8-based x72 DIMMs) VTT SDRAM I/O termination supply CK0–CK1 SDRAM clocks (positive line of differential pair) RFU Reserved for future use CK0–CK1 SDRAM clocks (negative line of differential pair) - - *The VDD and VDDQ pins are tied common to a single power-plane on these designs |
Similar Part No. - HMT164U6AFR6C-G8 |
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Similar Description - HMT164U6AFR6C-G8 |
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