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HMT125S6AFR8C-H9 Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HMT125S6AFR8C-H9 Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 51 page Rev. 0.2 / Dec. 2008 7 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2. Pin Architecture 2.1 Pin Definition Pin Name Description Pin Name Description CK[1:0] Clock Inputs, positive line 2 DQ[63:0] Data Input/Output 64 CK[1:0] Clock Inputs, negative line 2 DM[7:0] Data Masks 8 CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8 RAS Row Address Strobe 1 DQS[7:0] Data strobes complement 8 CAS Column Address Strobe 1 RESET Reset pin 1 WE Write Enable 1 TEST Logic Analyzer specific test pin (No connect on SODIMM) 1 S[1:0] Chip Selects 2 EVENT Temperature event pin 1 A[9:0], A11, A[15:13] Address Inputs 14 VDD Core and I/O power 18 A10/AP Address Input/Autoprecharge 1 VSS Ground 52 A12/BC Address Input/Burst Stop 1 VREFDQ Input/Output Reference 2 BA[2:0] SDRAM Bank Address 3 VREFCA ODT[1:0] On-die termination control 2 VDDSPD SPD and Temp sensor power 1 SCL Serial Presence Detect (SPD) Clock input 1 Vtt Termination voltage 2 SDA SPD Data Input/Output 1 NC Reserved for future use 2 SA[1:0] SPD address 2 Total 204 |
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