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HMT41GV7AMR4C-G7 Datasheet(PDF) 8 Page - Hynix Semiconductor |
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HMT41GV7AMR4C-G7 Datasheet(HTML) 8 Page - Hynix Semiconductor |
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8 / 35 page  Rev. 0.02 / Apr. 2009 8 DM0–DM8 IN Active High Masks write data when high, issued concurrently with input data. VDD, VSS Supply Power and ground for the DDR3 SDRAM input buffers, and core logic. VTT Supply Termination Voltage for Address/Command/Control/Clock nets. DQS0-DQS17 I/O Positive Edge Positive line of the differential data strobe for input and output data. DQS0–DQS17 I/O Negative Edge Negative line of the differential data strobe for input and output data. TDQS9-TDQS17 TDQS9-TDQS17 OUT TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Reg- ister A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask func- tion and TDQS is not used.x4/x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. SA0–SA2 — These signals are tied at the system planar to either VSS or VDDSPD to con- figure the serial SPD EEPROM address range. SDA I/O — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. SCL IN — This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pull up. VDDSPD Supply Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) opera- tion. EVENT OUT (open drain) Active Low This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level require- ment is met for the EVENT pin on TS/SPD part. RESET IN The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will remain synchronized with the input clock) Par_In IN Parity bit for the Address and Control bus.(“1”:Odd, “0”:Even) Err_Out OUT (open drain) Parity error detected on the Address and Control bus.A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs) Symbol Type Polarity Function |
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