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HMT125U6AFP8C-H8 Datasheet(PDF) 8 Page - Hynix Semiconductor |
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HMT125U6AFP8C-H8 Datasheet(HTML) 8 Page - Hynix Semiconductor |
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8 / 57 page  Rev. 0.1 / Dec 2008 8 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2.2 Input/Output Functional Description Symbol Type Polarity Function CK0–CK1 CK0–CK1 SSTL Differential crossing CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). CKE0–CKE1 SSTL Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. S0–S1SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is dis- abled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. RAS, CAS, WE SSTL Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered. ODT0–ODT1 SSTL Active High When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is enabled in the Mode Register 1 (MR1). VREFDQ Supply Reference voltage for SSTL15 I/O inputs. VREFCA Supply Reference voltage for SSTL 15 command/address inputs. VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA0–BA2 SSTL — Selects which SDRAM bank of eight is activated. A0–A13 SSTL — During a Bank Activate command cycle, Address input defines the row address (RA0–RA15). During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autopre- charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre- charged. If AP is low, autoprecharge is disabled. During a Precharge com- mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be per- formed (HIGH, no burst chop; LOW, burst chopped). DQ0–DQ63, CB0–CB7 SSTL — Data and Check Bit Input/Output pins. DM0–DM8 SSTL Active High DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. VDD, VSS Supply Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. |
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