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HMT31GR7BFR8A-H9 Datasheet(PDF) 10 Page - Hynix Semiconductor |
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HMT31GR7BFR8A-H9 Datasheet(HTML) 10 Page - Hynix Semiconductor |
10 / 76 page Rev. 0.2 / Feb. 2010 10 Registering Clock Driver Specifications Capacitance Values Input & Output Timing Requirements Symbol Parameter Conditions Min Typ Max Unit CI Input capacitance, Data inputs 1.5 - 2.5 pF Input capacitance, CK, CK, FBIN, FBIN 2 - 3 pF Input capacitance, CK, CK, FBIN, FBIN (DDR3-1600) 1.5 - 2.5 pF CIR Input capacitance, RESET, MIRROR, QCSEN VI = VDD or GND; VDD = 1.5v -- 3 pF Symbol Parameter Conditions DDR3-800 1066/1333 Unit Min Max fclock Input clock frequency Application frequency 300 670 Mhz fTEST Input clock frequency Test frequency 70 300 Mhz tSU Setup time Input valid before CK/CK 100 - ps tH Hold time Input to remain valid after CK/CK 175 - ps tPDM Propagation delay, single- bit switching CK/CK to output 0.65 1.0 ns tDIS Output disable time (1/2- Clock prelaunch) Yn/Yn to output float 0.5 tCK + tQSK1(min) -ps tEN Output enable time (1/2- Clock prelaunch) Output driving to Yn/Yn 0.5 tCK - tQSK1(max) -ps |
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Similar Description - HMT31GR7BFR8A-H9 |
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