PixArt Imaging Inc.

PAS6167

CMOS Image Sensor IC

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8

PixArt Imaging Inc.

V1.0,

2009/08/12

Data Transfer Format

Master transmits data to salve ( write cycle )

S : Start.

A : Acknowledge by salve.

P : Stop.

RW : The LSB of 1

Read cycle, RW = 0 – Write cycle.

SUBADDRESS : The address values of PAS6167 internal control registers. ( Please refer to

PAS6167 register description )

During write cycle, the master generates start condition and then places the 1

combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6167 )

issues acknowledgment, the master places 2

PAS6167 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6167

control register ( address was assigned by 2

can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6167

sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat

until last byte write. Every control registers value inside PAS6167 can be programming via this way.

Slave transmits data to master ( read cycle )

The sub-address was taken from previous write cycle.

The sub-address is automatically increment after each byte read.

Am : Acknowledge by master.

Note there is no acknowledgment from master after last byte read.

During read cycle, the master generates start condition and then place the 1

slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits

DATA was also placed on SDA line by PAS6167. The 8 bits data was read from PAS6167 internal control

register that address was assigned by previous write cycle. Follow the master acknowledgment, the

PAS6167 place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit

to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is

no longer generated by master but instead by keep SDA line high. The slave ( PAS6167 ) must releases

SDA line to master to generate STOP condition.