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VG36128401A Datasheet(PDF) 7 Page - Vanguard International Semiconductor |
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VG36128401A Datasheet(HTML) 7 Page - Vanguard International Semiconductor |
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7 / 69 page  Document : 1G5-0154 Rev.1 Page 7 VIS VG36128401A Preliminary VG36128801A VG36128161A CMOS Synchronous Dynamic RAM AC Characteristics : (Ta = 0 to 70°C V DD = 3.3V 0.3V, VSS = 0V) symbol A.C. Parameter -75 -8H unit note Min. Max. Min. Max. tRC Row cycle time 60 70 ns tRCD RAS to CAS delay 20 20 tRP Precharge to refresh/row activate command 15 20 tRRD Row activate to row activate delay 15 20 tRAS Row activate to precharge time 37.5 100,000 50 100,000 tCK2 Clock cycle time CL2 7.5 10 ns tCK3 CL3 7.5 10 tCH Clock high time 2.25 3 tCL Clock low time 2.25 3 tAC2 Access time from CLK (positive edge) CL2 5 6 tAC3 CL3 5 6 tT Transition time of CLK (Rise and Fall) 1 10 1 10 tCCD CAS to CAS Delay time 1 1 CLK tOH Data output hold time 2.5 3 ns tLZ Data output low impedance 0 0 tHZ2 Data output high impedance CL2 4 6 9 tHZ3 CL3 4 6 tIS Data/Address/Control Input setup time 1 2 tIH Data/Address/Control Input hold time 0.5 1 tSRX Minimum CKE ”High”for Self-Refresh exit 1 1 CLK tPDE Power Down Exit set-up time 2 2 ns tRSC Mode Register Set Cycle 2 2 CLK tDPL Data-in to precharge 2 1 CLK tDAL2 Data-in to ACT (REF) Command CL2 2clk+tRP 1clk+tRP ns tDAL3 CL3 2clk+tRP 1clk+tRP tBDL Last data in to burst stop 1 1 CLK tREF Refresh time 64 64 ms ± |
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