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VG36643241BT-10 Datasheet(PDF) 1 Page - Vanguard International Semiconductor |
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VG36643241BT-10 Datasheet(HTML) 1 Page - Vanguard International Semiconductor |
1 / 72 page Document : 1G5-0099 Rev.1 Page 1 VIS Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM Description The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 - bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package. Features • Single 3.3V ( ) power supply • High speed clock cycle time : 8/10 for LVTTL • High speed clock cycle time : 8/10 for SSTL - 3 • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wrap sequence (Sequential/Interleave) • Automatic precharge and controlled precharge • Auto refresh and self refresh modes • Dual Internal banks controlled by A11 (Bank select) for VG36643211(2) • Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2) • Each Banks can operate simultaneously and independently • LVTTL compatible I/O interface for VG36643211 and VG36643241 • SSTL - 3 compatible I/O interface for VG36643212 and VG36643242 • Random column access in every cycle • x32 organization • Input/Output controlled by DQM0 ~ 3 • 4,096 refresh cycles/64ms • Burst termination by burst stop and precharge command • Burst read/single write option 0.3V ± |
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