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VG4632321AQ-5R Datasheet(PDF) 1 Page - Vanguard International Semiconductor |
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VG4632321AQ-5R Datasheet(HTML) 1 Page - Vanguard International Semiconductor |
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1 / 81 page  Document: Rev.1 Page 1 VIS Preliminary VG4632321A 524,288x32x2-Bit CMOS Synchronous Graphic RAM Overview The VG4632321A SGRAM is a high-speed CMOS synchronous graphic RAM containing 32M bits. It is internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit bank is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The VG4632321A provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, it features the write per bit and the masked block write functions. By having a programmable Mode register and special mode register, the system can choose the best suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, and when combined with special graphics functions result in a device particularly well suited to high performance graphics applications. Features • Fast access time from clock: 4.5/5/5.5/6/7ns • Fast clock rate: 222/200/183/166/143MHz • Fully synchronous operation • Internal pipelined architecture • Dual internal banks(512K x 32-bit x 2-bank) • Programmable Mode and Special Mode registers - CAS Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst Read Single Write - Load Color or Mask register • Burst stop function • Individual byte controlled by DQM0-3 • Block write and write-per-bit capability • Auto Refresh and Self Refresh • 2048 refresh cycles/32ms • Single + 3.3V power supply • Interface: LVTTL • JEDEC 100-pin Plastic QFP package 0.3V ± DQ3 1 VDDQ 2 DQ4 3 DQ5 4 VSSQ 5 DQ6 6 DQ7 7 VDDQ 8 DQ16 9 DQ17 10 11 DQ18 12 DQ19 13 VDDQ 14 15 16 17 DQ21 18 19 VSSQ 20 DQ23 21 22 DQM0 23 24 WE 25 CAS 26 RAS 27 CS 28 BS 29 A9 30 DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS DQ11 DQ10 DQ9 DQ8 NC DQM3 DQM1 CLK CKE DSF NC A8/AP VSSQ VDD VSS DQ20 DQ22 VDDQ DQM2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQ24 VDD VSSQ VDDQ Pin Assignment (Top View) Key Specifications VG4632321A -4.5/-5/-5.5/-6/-7 tCK Clock Cycle time(min.) 4.5/5/5.5/6/7 ns tRAS Row Active time(min.) 40/40/40/42/42 ns tAC Access time from CLK(max.) 4/4.5/5/5.5/6 ns tRC Row Cycle time(min.) 55/55/56.5/60/62 ns |
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