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MAX1241AMJA+ Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX1241AMJA+ Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 15 page End of conversion (EOC) is signaled by DOUT going high. DOUT’s rising edge can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on SCLK’s falling edge. The next falling clock edge pro- duces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 12 data bits and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occur- ring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros at DOUT and have no effect on converter operation. Minimum cycle time is accomplished by using DOUT’s rising edge as the EOC signal. Clock out the data with 12.5 clock cycles at full speed. Pull CS high after read- ing the conversion’s LSB. After the specified minimum time (tCS), CS can be pulled low again to initiate the next conversion. Output Coding and Transfer Function The data output from the MAX1240/MAX1241 is binary, and Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successive- integer LSB values. If VREF = +2.500V, then 1 LSB = 610µV or 2.500V/4096. ____________Applications Information Connection to Standard Interfaces The MAX1240/MAX1241 serial interface is fully compat- ible with SPI/QSPI and MICROWIRE standard serial interfaces (Figure 11). If a serial interface is available, set the CPU’s serial interface in master mode so the CPU generates the ser- ial clock. Choose a clock frequency up to 2.1MHz. 1) Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2) Wait the for the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT rising edge to determine the end of conversion. 3) Activate SCLK for a minimum of 13 clock cycles. The first falling clock edge produces the MSB of the DOUT conversion. DOUT output data transitions on SCLK’s falling edge and is available in MSB-first for- mat. Observe the SCLK to DOUT valid timing char- acteristic. Data can be clocked into the µP on SCLK’s rising edge. 4) Pull CS high at or after the 13th falling clock edge. If CS remains low, trailing zeros are clocked out after the LSB. +2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO ______________________________________________________________________________________ 11 11 …111 11 …110 11 …101 00 …011 00 …010 00 …001 00 …000 01 2 FS OUTPUT CODE FS - 3/2LSB INPUT VOLTAGE (LSBs) FS = VREF - 1LSB 1LSB = VREF 4096 FULL-SCALE TRANSITION 3 … … … … CS SCLK DOUT INTERNAL T/H (TRACK/ACQUIRE) tCS0 tCONV tDV tAPR tSTR (HOLD) (TRACK/ACQUIRE) B2 B1 B0 tCH tDO tCL tTR tCS Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF - 1LSB, Zero Scale (ZS) = GND Figure 9. Detailed Serial-Interface Timing |
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