______________________________________________________________________________________ 11

1.0625Gbps to 11.3Gbps, SFP+ Laser Driver

with Laser Impedance Mismatch Tolerance

Pin Description (continued)

Figure 2. Functional Diagram

EYE SAFETY AND

OUTPUT CONTROL

TOUT+

TOUT-

BIAS

BMON

TX_EN

TX_POL

50I

50I

FAULT

TIN+

TIN-

SDA

SCL

CSEL

DISABLE

BMAX

LASER BIAS

CURRENT LIMITER

POWER-ON RESET

7.5kI

75kI

1

0

PW

CONTROL

25I

25I

EQ

100

3-WIRE

INTERFACE

REGISTER

CONTROL

LOGIC

SET_TXEQ

SET_PWCTRL

75kI

75kI

9b DAC SET_IMOD

6b DAC SET_TXDE

9b DAC SET_IBIAS

MAX3946

PIN

NAME

FUNCTION

18

SCL

Serial-Clock Input, CMOS. This pin has 75kI internal pulldown.

19, 24

Ground

20, 23

Power-Supply Connections. Provides supply voltage to the core circuitry.

21

TIN+

Noninverted Data Input

22

TIN-

Inverted Data Input

—

EP

Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical

performance (see the Exposed-Pad Package and Thermal Considerations section).