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TPS53127PW Datasheet(PDF) 5 Page - Texas Instruments |
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TPS53127PW Datasheet(HTML) 5 Page - Texas Instruments |
5 / 23 page TPS53127 www.ti.com SLVSA93 – MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SW1 = 0.7 V, TA = 25°C, TOFF1L CH1 min off time 216 ns VFB1 = 0.7 V SW2 = 0.7 V, TA = 25°C, TOFF2L CH2 min off time 216 ns VFB2 = 0.7 V SOFT START ISSC SS1/SS2 charge current VSS1/VSS2 = 0 V, TA = 25°C –1.5 –2 –2.5 mA TCISSC ISSC temperature coefficient On the basis of 25°C(1) –4 3 nA/°C ISSD SS1/SS2 discharge current VSS1/VSS2 = 0.5 V 100 150 mA UVLO Wake up 3.7 4.0 4.3 VUV5VFILT V5FILT UVLO threshold V Hysteresis 0.2 0.3 0.4 LOGIC THRESHOLD VENH ENx high-level input voltage EN 1/2 2.0 V VENL ENx low-level input voltage EN 1/2 0.3 V CURRENT SENSE ITRIP TRIP source current VTRIPx = 0.1 V, TA = 25°C 8.5 10 11.5 mA TCITRIP ITRIP temperature coefficient On the basis of 25°C 4000 ppm/°C (VTRIPx-GND-VPGNDx-SWx) voltage, –15 0 15 VTRIPx-GND = 60 mV, TA = 25°C VOCLoff OCP compensation offset mV (VTRIPx-GND-VPGNDx-SWx) voltage, –20 20 VTRIPx-GND = 60 mV VRtrip Current limit threshold setting range VTRIPx-GND voltage 30 300 mV OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold OVP detect 110 115 120 % TOVPDEL Output OVP prop delay 1.5 ms UVP detect 65 70 75 VUVP Output UVP trip threshold % Hysteresis (recover < 20 ms) 10 TUVPDEL Output UVP delay 17 30 40 ms TUVPEN Output UVP enable delay UVP enable delay / soft-start time x1.4 x1.7 x2.0 ms THERMAL SHUTDOWN Shutdown temperature (2) 150 TSDN Thermal shutdown threshold °C Hysteresis (2) 20 (2) Not production tested - ensured by design. TERMINAL FUNCTIONS PIN Fucntion Table TERMINAL I/O DESCRIPTION QFN TSSOP NAME 24 24 Supply input for high-side NFET driver. Bypass to SWx with a high-quality VBST1, 23, 8 2, 11 I 0.1-mF ceramic capacitor. An external schottky diode can be added from VBST2 VREG5 if forward drop is critical to drive the high-side FET. EN1, EN2 24, 7 3, 10 I Enable. Pull High to enable SMPS. Output voltage inputs for on-time adjustment and output discharge. Connect VO1, VO2 1, 6 4, 9 I directly to the output voltage. VFB1, 2, 5 5, 8 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider. VFB2 Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS53127 |
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