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BLOCK DIAGRAM

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PIN CONFIGRATION

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PIN FUNCTION

PIN No.

PIN name

PIN Function

1

VTT_IN

Termination power supply pin

2

GND

Ground pin

3

REF

Reference voltage output pin

4

VTT

Termination output pin

5

N.C.

Non connection

6

VCC

VCC Pin

7

N.C.

Non connection

8

N.C.

Non connection

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Description of operations

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VCC

In BD3537F, an independent power input pin is provided for an internal circuit operation of the IC. This is used to drive the

amplifier circuit of the IC, and its maximum current rating is 2.5mA.

The power supply voltage is 5.0 volts.

It is

recommended to connect a bypass capacitor of 1μF or so to VCC.

・

VTT_IN

VTT_IN is a power supply input pin for VTT output. Voltage in the range up to 1.8 volts may be supplied to this VTT_IN

terminal, but care must be taken to the current limitation due to on-resistance of the IC and the change in allowable loss due to

input/output voltage difference.

Higher impedance of the voltage input at VTT_IN may result in oscillation or degradation in ripple rejection, which must be

noted. To VTT_IN terminal, it is recommended to use a 10μF capacitor characterized with less change in capacitance. But

it may depend on the characteristics of the power supply input and the impedance of the pc board wiring, which must be

carefully checked before use.

・

VTT

A DDR memory termination output pin. BD3537F has a sink/source current capability of ±1.8A respectively. The output

voltage is same as REF voltage. VTT output is turned to OFF when VCC UVLO or thermal shutdown protector is activated

with EN pin level becomes EN-OFF voltage or below. Do not fail to connect a capacitor to VTT output pin for a loop gain

phase compensation and a reduction in output voltage variation in the event of sudden change in load. Insufficient

capacitance may cause an oscillation. High ESR (Equivalent Series Resistance) of the capacitor may result in increase in

output voltage variation in the event of sudden change in load. It is recommended to use a 10 μF ceramic capacitor (X5R or

X7R), though it depends on ambient temperature and other conditions. A low ESR ceramic capacitor may reduce a loop gain

phase margin and may cause an oscillation, which may be improved by connecting a resistor in series with the OS-capacitor

(several-hundred μF).

・

REF

With an input of 0.6 volts or higher, the level at REF pin turns to “High” to provide VTT output. If the input is lowered to 0.15

volts or less, the level at REF pin turns to “Low” and VTT status turns to Hi-Z.

VCC

VCC

VDDQ

VTT

Reference

Block

GND

VTT

VTT_IN

TSD

EN

UVLO

UVLO

TSD

VCC

VCC

TSD

EN

UVLO

-

+

-

+

+

-

C3

REF

VTT_IN

C2

C1

Enable

Block

EN

C4

R1

R2

Thermal

Protection

N.C

VTT_IN

GND

REF

N.C.

VCC

1

2

3

6

7

8

VTT

N.C.

4

5