BD8153EFV

Technical Note

9/17

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2009.07 - Rev.B

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In the current mode control, since the coil current is controlled, a pole (phase lag) made by the CR filter composed of the

output capacitor and load resistor will be created in the low frequency range, and a zero (phase lead) by the output

capacitor and ESR of capacitor will be created in the high frequency range. In this case, to cancel the pole of the power

the illustration.

Open loop gain characteristics

Pole at the power amplification stage

When the output current reduces, the load resistance

Error amp phase

compensation characteristics

Zero at the power amplification stage

When the output capacitor is set larger, the pole

frequency lowers but the zero frequency will not

change. (This is because the capacitor ESR

becomes 1/2 when the capacitor becomes 2 times.)

It is possible to realize the stable feedback loop by canceling the pole fp(Min.), which is created by the output capacitor

and load resistor, with CR zero compensation of the error amp as shown below.

fz(Amp.) = fp(Min.)

1

=

1

2

  Rc  Cc

2

  Romax  Co

1

Fp =

2

1

fz(ESR) =

2

1

fp(Min) =

2

[Hz]

 at light load

1

fz(Max) =

2

[Hz]

 at heavy load

1

fp(Amp.) =

2

fp(Min)

fp(Max)

fz(ESR)

A

0

-90

0

Gain

[dB]

Phase

[deg]

0

0

A

-90

Gain

[dB]

Phase

[deg]

L

Rc

Cc

Cin

Vcc,PVcc

GND,PGND

SW

COMP

Co

ESR

Ro

Vo

Fig. 29 Gain vs Phase

Fig. 30 Application Circuit Diagram

[Hz]

[Hz]

[Hz]

[Hz]