BD8904F, BD8904FV, BD8905F, BD8906F, BD8906FV, BD8907F

Technical Note

4/15

www.rohm.com

2009.07 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

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Pin Description

Pin No.

Pin Name

I/O

Signal Level

Pin Function

1

CLKDIV1

I

VDD

Clock frequency selection input 1

2

CLKDIV2

I

VDD

Clock frequency selection input 2

3

VSEL

I

VDD

Card supply voltage selection input; “H”: VREG=5V, “L”: VREG=3V

4

PGND

S

GND

GND for charge pump

5

S2

I/O

-

Capacitor connection for charge pump

(between S1/S2): C = 100nF (ESR < 100mΩ)

6

VDDP

S

VDDP

Power supply for charge pump

7

S1

I/O

-

Capacitor connection for charge pump

(between S1/S2): C = 100nF (ESR < 100mΩ)

8

VCH

I/O

-

Charge pump output: Decoupling capacitor;

Connect C = 100nF (ESR < 100mΩ) between VCH and PGND

9

PRESB

I

VDD

Card presence contact input (active “L”)

When PRES or PRESB is active, the card is considered ‘present’ and a

built-in debounce feature of 8ms (typ.) is activated.

Pulled up to VDD with a 2MΩ resistor.

10

PRES

I

VDD

Card presence contact input (active “H”)

When PRES or PRESB is active, the card is considered ‘present’ and a

built-in debounce feature of 8ms (typ.) is activated.

Pulled down to GND with a 2MΩresistor.

11

IO

I/O

VREG

Card contact I/O data line; Pulled up to VREG with a 11kΩ resistor

12

AUX2

I/O

VREG

Card contact I/O data line; Pulled up to VREG with a 11kΩ resistor

13

AUX1

I/O

VREG

Card contact I/O data line; Pulled up to VREG with a 11kΩ resistor

14

CGND

S

GND

GND

15

CLK

O

VREG

Card clock output

16

RST

O

VREG

Card reset output

17

VREG

O

VREG

Card supply voltage; Connect a capacitor (ESR < 100mΩ) of 100nF -

220nF between VREG and CGND

18

(BD8904F)

(BD8904FV)

(BD8905F)

PORADJ

I

-

Power-on reset threshold adjustment voltage input ; set with an external

resistor bridge

18

(BD8906F)

(BD8906FV)

(BD8907F)

TEST

Normally used OPEN. Input voltage range: 0V - VDD voltage

Can also be used at VDD or GND potential.

19

CMDVCCB

I

VDD

Activation sequence command input; The activation sequence starts by

signal input (H→L) from the host

20

RSTIN

I

VDD

Card reset signal input

21

VDD

S

VDD

Input power source pin

22

GND

S

GND

GND

23

OFFB

O

VDD

Alarm output pin (active “L”)

24

XTAL1

I

VDD

Crystal connection or input for external clock

25

XTAL2

O

VDD

Crystal connection (leave open pin when external clock source is used)

26

IOC

I/O

VDD

Host data I/O line; Pulled up to VDD with a 11kΩ resistor

27

AUX1C

I/O

VDD

Host data I/O line; Pulled up to VDD with a 11kΩ resistor

28

AUX2C

I/O

VDD

Host data I/O line; Pulled up to VDD with a 11kΩ resistor