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REV. A

■ Outer Dimentions

Fig.1．

SOP-J14

■ Block Diagram

■ Pin Number / Pin Name

Fig.2．

Block diagram

No.

Pin Name

No.

Pin Name

1

CVBS_IN

8

LPF_SEL

2

VREF

9

PR_OUT

3

PY_IN

10

PB_OUT

4

PB_IN

11

GND

5

PR_IN

12

PY_OUT

6

MUTE1

13

VCC

7

MUTE2

14

CVBS_OUT

BH76071FJ

Lot No.

1

2

3

4

5

6

7

8

10

14

13

12

11

BIAS

CLAMP

13.5MHz

LPF

REF

MUTE1

LPF_SEL

6.75MHz

LPF

75Ω

6dB

75Ω

6dB

75Ω

6dB

75Ω

6dB

HD

SD

CVBS_OUT

PR _IN

PB _IN

PY _IN

VREF

CVBS_IN

PY _OUT

GND

30MHz

LPF

13.5MHz

LPF

30MHz

LPF

13.5MHz

LPF

30MHz

LPF

HD

SD

HD

SD

PB _OUT

PR _OUT

VCC

MUTE2

CLAMP

BIAS

MUTE1

MUTE2

9

MUTE2

MUTE2

※ : Please use the impedance of the circuit connected

to the input terminals(1 and 3pin) at 1kΩ or less.