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BU2506FV-E2 Datasheet(PDF) 2 Page - Rohm |
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BU2506FV-E2 Datasheet(HTML) 2 Page - Rohm |
2 / 9 page BU2506FV,BU2505FV Technical Note 2/8 www.rohm.com 2009.06 - Rev.A © 2009 RzOHM Co., Ltd. All rights reserved. ● Electrical Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Parameter Symbol Limits Unit Conditions MIN. TYP. MAX. <Digital unit> Power source current ICC - 0.85 2.8 mA At CLK=10MHz, IAO=0μA Input leak current IILK -5 - 5 μA VIN=0 to VCC Input voltage L VIL - - 0.8 V - Input voltage H VIH 2.0 - - V - Output voltage L VOL 0 - 0.4 V IOL=2.5mA Output voltage H VOH 4.6 - 5 V IOH=-2.5mA <Analog unit> Consumption current IrefH - 4.5 7.5 mA Data condition : at maximum current - 3.7 6.2 mA (*1) D/A converter upper standard voltage setting range VrefH 3.0 - 5 V Outputs are not necessarily within the standard voltage setting range, but ARE within the buffer amplifier output voltage range (VO). D/A converter lower standard voltage setting range VrefL 0 - 1.5 V Buffer amplifier output voltage range VO 0.1 - 4.9 V IO=±100μA 0.2 - 4.75 IO=±1.0mA Buffer amplifier output drive range IO -2 - 2 mA Upper saturation voltage =0.35V Lower saturation voltage =0.23V Precision Differential non-linearity error DNL -1.0 - 1.0 LSB VrefH =4.796V VrefL=0.7V VCC=5.5V (4mV/LSB) At no load (IO=+0mA ) Integral non-linearity error INL -3.5 - 3.5 Zero point error SZERO -25 - 25 mV Full scale error SFULL -25 - 25 Buffer amplifier output impedance RO - 5 15 Ω - Pull-up I/O internal resistance value Rup 12.5 25 37.5 kΩ Input voltage 0V (Resistance value changes according to voltage supplied) *1 Value in the case where CH1 ~ CH8 are set to maximum current ● Timing Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃) Parameter Symbol Limits Unit Conditions MIN. TYP. MAX. Judgment level is 80% / 20% of VCC. Reset L pulse width tRTL 50 - - nS - Clock L pulse width tCKL 50 - - - Clock H pulse width tCKH 50 - - - Clock rise time tcr - - 50 - Clock fall time tcf - - 50 - Data setup time tDCH 20 - - - Data hold time tCHD 40 - - - Load setup time tCHL 50 - - - Load hold time tLDC 50 - - - Load H pulse width tLDH 50 - - - Data output delay time tDO - - 90 CL=100pF DA output settling time tLDD - 7 20 μS CL≦1000pF, VO:0.5V⇔4.5V . Until output becomes the final value 1/2LSB CLK DI LD DA OUTPUT tCKL tcr tCKH tcf tDCH tCHD tCHL tLDH tLDC tLDD DO OUTPUT tDo RESET tRTL |
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