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SS810-26GU Datasheet(PDF) 7 Page - Silicon Standard Corp.

Part # SS810-26GU
Description  3-Pin Microprocessor Reset Circuits
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Manufacturer  SSC [Silicon Standard Corp.]
Direct Link  http://www.siliconstandard.com
Logo SSC - Silicon Standard Corp.

SS810-26GU Datasheet(HTML) 7 Page - Silicon Standard Corp.

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SS809/810G
9/20/2006 Rev.3.01
DETAILED DESCRIPTIONS OF TECHNICAL TERMS
RESET OUTPUT
The µP will be activated at a valid reset state. These
µP supervisory circuits assert reset to prevent code
execution errors during power-up, power-down, or
brownout conditions.
RESET is guaranteed to be a logic low for
VTH>VCC>0.9V. Once VCC exceeds the reset
threshold, an internal timer keeps RESET low for
the reset timeout period; after this interval, RESET
goes high.
If a brownout condition occurs (VCC drops below the
reset threshold), RESET goes low. Any time VCC
goes below the reset threshold, the internal timer
resets to zero, and RESET goes low. The internal
timer is activated after VCC returns above the reset
threshold, and RESET remains low for the reset
timeout period.
BENEFITS
OF
HIGHLY
ACCURATE
RESET
THRESHOLD
The SS809G and SS810G with specified voltage as 5V
±
10% or 3V
±10% are ideal for systems using a 5V±5%
or 3V
±5% power supply. The reset is guaranteed to
assert after the power supply falls out of regulation,
but before the power drops below the minimum
specified operating voltage range of the system ICs.
The pre-trimmed thresholds reduce the range over
which an undesirable reset may occur.
APPLICATION INFORMATION
NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the
µP during
power-up, power-down, and brownout conditions, the
SS809G series are relatively resistant to short-duration
negative-going VCC transients.
ENSURING A VALID RESET OUTPUT DOWN TO
VCC=0
When VCC falls below 0.9V, the SS809G RESET
output no longer sinks current; it becomes an open
circuit. In this case, high-impedance CMOS logic
inputs
connected
to
RESET
can
drift
to
undetermined voltages. Therefore, the SS809G/810G
are perfect for most CMOS applications down to VCC
of 0.9V. However in applications where RESET
must be valid down to 0V, adding a pull-down resistor
to RESET causes any leakage currents to flow to
ground, holding RESET low.
INTERFACING TO A MICROPROCESSOR WITH
BIDIRECTIONAL RESET PINS
The RESET output on the SS809N is open drain,
and this device interfaces easily with
µPs that have
bidirectional
reset
pins.
Connecting
the
µP
supervisor’s
RESET
output
directly
to
the
microcontroller’s RESET pin with a single pull-up
resistor allows either device to assert reset.


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