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X25043VI Datasheet(PDF) 4 Page - Xicor Inc. |
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X25043VI Datasheet(HTML) 4 Page - Xicor Inc. |
4 / 15 page X25043/45 4 Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25043/45, followed by the 8-bit byte address. Bit 3 of the Read instruction contains address A8. This bit is used to select the upper or lower half of the device. After the read opcode and byte address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The byte address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($1FF) the address counter rolls over to address $000, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM Array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the read status register opcode is sent, the contents of the status register is shifted out on the SO line as shown in Figure 2. Write Sequence Prior to any attempt to write data into the X25043/45 the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25043/45. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction the write operation will be ignored. To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. Bit 3 of the Write instruction contains address A8. This bit is used to select the upper or lower half of the device. This is minimally a twenty-four clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to four bytes of data to the X25043/45. The only restriction is the four bytes must reside on the same page. A page address begins with address X XXXX XX00 and ends with X XXXX XX11. If the byte address counter reaches X XXXX XX11 and the clock continues the counter will roll back to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought HIGH after the twenty-fourth, thirty-second, fortieth, or forty-eighth clock. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figure 4 and 5 below for a detailed illustration of the write sequences. While the write is in progress, following a status register or E2PROM write sequence the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH and all other bits in the status register will be undefined. RESET/RESET Operation The RESET (X25043) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the Watchdog timer has reached its pro- grammable time-out limit. Table 1. Instruction Set Instruction Name Instruction Format* Operation WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations) WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations) RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register (Block Lock Bits) READ 0000 A8011 Read Data from Memory Array beginning at selected address WRITE 0000 A8010 Write Data to Memory Array beginning at Selected Address (1 to 4 Bytes) 3844 PGM T05.1 *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. |
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