X25043/45

3

PRINCIPLES OF OPERATION

interface directly with the synchronous serial peripheral

interface (SPI) of many popular microcontroller families.

The X25043/45 contains an 8-bit instruction register. It

is accessed via the SI input, with data being clocked in

on the rising SCK.

CS must be LOW and WP input must

be HIGH during the entire operation. The X25043/45

monitors the bus and provides a

RESET/RESET output

if there is no bus activity within the preset time period.

Table 1 contains a list of the instructions and their

operation codes. All instructions, addresses and data

are transferred MSB first. Bit 3 of the Read and Write

Data input is sampled on the first rising edge of SCK after

CS goes LOW. SCK is static, allowing the user to stop

the clock and then resume operations.

Write Enable Latch

The X25043/45 contains a “write enable” latch. This

latch must be SET before a write operation will be

completed internally. The WREN instruction will set the

latch and the WRDI instruction will reset the latch. This

latch is automatically reset upon a power-up condition

and after the completion of a byte, page, or status

register write cycle. The latch is also reset if

WP is

brought LOW.

Status Register

The RDSR instruction provides access to the status

register. The status register may be read at any time,

even during a write cycle. The status register is format-

ted as follows:

7

6

5

4

321

0

X

X

WD1 WD0

BL1

BL0

WEL

WIP

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When issuing, WREN, WRDI and RDSR commands, it

is not necessary to send a byte address or data.

The Write-In-Process (WIP) bit indicates whether the

X25043/45 is busy with a write operation. When set to a

“1”, a write is in progress, when set to a “0”, no write is

in progress. During a write, all other bits are set to “1”.

The WIP bit is read-only.

The Write Enable Latch (WEL) bit indicates the status of

the “write enable” latch. When set to a “1”, the latch is set,

when set to a “0”, the latch is reset. The WEL bit is read-

only and is set by the WREN instruction and reset by

WRDI instruction or successful completion of a write

cycle.

The Block Protect (BL0 and BL1) bits indicate the extent

of protection employed. These nonvolatile bits are set by

issuing the WRSR instruction and allows the user to

select one of four levels of protection and program the

watchdog timer. The X25043/45 is divided into four

1024-bit segments. One, two, or all four of the segments

may be locked. That is, the user may read the segments

but will be unable to alter (write) data within the selected

segments. The partitioning is controlled as illustrated

below with the state of BL1 and BL0.

Status Register Bits

Array Addresses

BL1

BL0

Protected

0

0

None

0

1

$180–$1FF

1

0

$100–$1FF

1

1

$000–$1FF

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The Watchdog Timer (WD0 and WD1) bits allow setting

of the watchdog time-out function as shown in the table

below. These nonvolatile bits are set by issuing the

WRSR instruction.

Status Register Bits

Watchdog Time-out

WD1

WD0

(Typical)

0

0

1.4 Seconds

0

1

600 Milliseconds

1

0

200 Milliseconds

1

1

Disabled

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