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X25F087P Datasheet(PDF) 2 Page - Xicor Inc. |
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X25F087P Datasheet(HTML) 2 Page - Xicor Inc. |
2 / 13 page X25F087 2 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be programmed to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25F087 is deselected and the SO output pin is at high impedance and unless a nonvol- atile write cycle is underway, the X25F087 will be in the standby power mode. CS LOW enables the X25F087, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Program Protect (PP) When PP is LOW, nonvolatile writes to the X25F087 are disabled, but the part otherwise functions normally. When PP is held HIGH, all functions, including nonvolatile writes, operate normally. PP going LOW while CS is still LOW will interrupt a programming cycle to the X25F087. If the nonvolatile write cycle has already been initiated, PP going low will have no affect on this cycle. PIN CONFIGURATION PIN NAMES 7007 FRM T01 PRINCIPLES OF OPERATION The X25F087 is a 1024 x 8 SerialFlash designed to inter- face directly with the synchronous Serial Peripheral Inter- face (SPI) of many popular microcontroller families. The X25F087 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the PP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume opera- tions where left off. Program Enable Latch The X25F087 contains a “Program Enable” latch. This latch must be SET before a program operation is initi- ated. The PREN instruction will set the latch and the PRDI instruction will reset the latch (Figure 4). This latch is automatically reset upon a power-up condition and after the completion of a sector program cycle. Block Lock Protection There are eight Block Lock Protection options. The pre- defined blocks and associated address ranges are pro- tected by programming the appropriate two byte Program Status instruction to the device (Table 1 and Figure 6). Once a Block Lock protect instruction has been completed, that Block Lock Protection setup is held in a nonvolatile Status Register (Figure 1) until the next Program Status instruction is issued. The sections of the memory array that are Block Lock protected can be read but not programmed until Block Lock Protection is removed or changed. SCK SI VSS PP NC VCC CS SO 1 2 3 4 8 7 6 5 8 PIN TSSOP VCC NC SCK SI 7007 FRM 02 CS SO PP VSS 1 2 3 4 8 7 6 5 8 PIN SOIC/DIP X25F087 X25F087 *0.197" *0.244" 0.122" 0.252" Not to scale *SOIC Measurement Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input PP Program Protect Input VSS Ground VCC Supply Voltage NC No Connect |
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