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X88C75PI Datasheet(PDF) 7 Page - Xicor Inc. |
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X88C75PI Datasheet(HTML) 7 Page - Xicor Inc. |
7 / 27 page X88C75 SLIC® E2 7 Figure 7. On-Chip Registers Programmable Address Decoding The X88C75 features an internal programmable ad- dress decoder which allows the nonvolatile memory array and the internal registers to be mapped in various locations of the 64K-byte memory map. The register set is mappable into a 1K-byte block, while the nonvolatile memory array is mappable into an 8K-byte block. The mapping is controlled by two nonvolatile configuration registers, the SFR Map Register and the E2 Memory Map Register. Their bits are mapped as follows: SFR Map Register (SFRM) Default = 3F 0 0 A15 A14 A13 A12 A11 A10 76 2887 ILL F10 543 21 0 A15-A10 The A15-A10 are upper address bits for the 1K-byte page where the SFR memory is mapped. 0 2887 ILL F30.2 0 LAM 0 RST A15 A14 A13 76543210 FC38 EEM* E2 Memory Map Register MSB LSB FC08 PDRB Port Data Register B MSB LSB FC10 PDRA Port Data Register A INT INTA INTB ENA ENB ENEE 0 EOW FC18 ISR Interrupt Status Register IRST 1 AWO BWO DIRA DIRB STRA STRB FC20 CR Configuration Register MSB LSB FC28 PPRB Port Pin Register B MSB LSB FC30 PPRA Port Pin Register A Special Function Register Memory Map Register 0 NOTE: * The value returned by reading these registers is the complement of the actual data. These registers are nonvolatile and a special SDP sequence is used to alter their contents. All the other registers are initialized by a valid reset input signal and when the device is power cycled. 0 A15 A14 A13 A12 A11 A10 FC00 SFRM* FE00 FE0F 16 Bytes General Purpose SRAM MSB LSB MSB LSB |
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