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X84161S8I-1.8 Datasheet(PDF) 3 Page - Xicor Inc. |
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X84161S8I-1.8 Datasheet(HTML) 3 Page - Xicor Inc. |
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3 / 18 page  X84161/641/129 3 DEVICE OPERATION The X84161/641/129 are serial EEPROMs designed to interface directly with most microprocessor buses. Stan- dard CE, OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive data and commands serially. Data Timing Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs first. Data output on the l/O line is active whenever both OE and CE are LOW. Care should be taken to ensure that WE and OE are never both LOW while CE is LOW. Read Sequence A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle between the write cycles. The address is sent serially, most signifi- cant bit first, over the I/O line. Note that this sequence is fully static, with no special timing restrictions, and the pro- cessor is free to perform other tasks on the bus when- ever the device CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, writing a ‘1’ will terminate the read sequence and enter the low power standby state, other- wise the device will await further reads in the sequential read mode. Sequential Read The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address in the array is reached, the address counter rolls over to address $0000 and reading may be continued indefinitely. Reset Sequence The reset sequence resets the device and sets an inter- nal write enable latch. A reset sequence can be sent at any time by performing a read/write “0”/read operation (see Figs. 1 and 2). This breaks the multiple read or write cycle sequences that are normally used to read from or write to the part. The reset sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write “0” cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence (which includes the address) is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the device initiates these operations properly. Figure 1. Read Sequence CE OE WE I/O (IN) "0" RESET WHEN ACCESSING: X84161 ARRAY: A15–A11=0 X84641 ARRAY: A15–A13=0 X84129 ARRAY: A15–A14=0 LOAD ADDRESS READ DATA A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O (OUT) 7008 FRM F04.1 D7 D6 D5 D4 D3 D2 D1 D0 |
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