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X4005M8-1.8 Datasheet(PDF) 2 Page - Xicor Inc. |
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X4005M8-1.8 Datasheet(HTML) 2 Page - Xicor Inc. |
2 / 18 page X4003/X4005 Characteristics subject to change without notice. 2 of 18 REV 1.1.3 4/30/02 www.xicor.com PIN CONFIGURATION NC VSS VCC SDA SCL 3 2 4 1 6 7 5 8 NC WP RESET 8-Pin JEDEC SOIC, MSOP PIN DESCRIPTION Pin (SOIC/DIP) Pin TSSOP Pin (MSOP) Name Function 1 3 NC No internal connections 2 4 NC No internal connections 3 5 2 RESET/ RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET/ RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a stop condition resets the watchdog timer. RESET/RESET goes active on power up and remains active for 250ms after the power supply stabilizes. 46 3 VSS Ground 5 7 4 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop condition resets the watchdog timer. The absence of this procedure with- in the watchdog time out period results in RESET/RESET going active. 6 8 5 SCL Serial Clock. The serial clock controls the serial bus timing for data input and output. 71 6 WP Write Protect. WP HIGH prevents changes to the watchdog timer setting. 82 1 VCC Supply voltage |
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