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X40014V8I-C Datasheet(PDF) 10 Page - Xicor Inc. |
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X40014V8I-C Datasheet(HTML) 10 Page - Xicor Inc. |
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10 / 25 page  X40010/X40011/X40014/X40015 – Preliminary Characteristics subject to change without notice. 10 of 25 REV 1.3.4 7/12/02 www.xicor.com Read Operation Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immedi- ately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 12 for the address, acknowledge, and data transfer sequence. Figure 9. Read Sequence Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write oper- ation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 12. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Ran- dom Reads, and Sequential Reads. Current Address Read Internally the device contains an address counter that maintains the address of the last word read incre- mented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The mas- ter terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See Figure 13 for the address, acknowledge, and data transfer sequence. 0 Slave Address Byte Address A C K A C K S t a r t S t o p Slave Address Data A C K 1 S t a r t SDA Bus Signals from the Slave Signals from the Master 10 1 0 0 1 1 1 1 1 111 1 |
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