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X84129PI-1.8 Datasheet(PDF) 1 Page - Xicor Inc. |
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X84129PI-1.8 Datasheet(HTML) 1 Page - Xicor Inc. |
1 / 18 page ©Xicor, Inc. 1994, 1997Patents Pending 7008-1.2 8/26/97 T2/C0/D0 SH 1 Characteristics subject to change without notice APPLICATION NOTE A V A I L A B L E 16K/64K/128K MPS™ EEPROM µPort Saver EEPROM FEATURES • Up to 10MHz data transfer rate • 25ns Read Access Time • Direct Interface to Microprocessors and Microcontrollers —Eliminates I/O port requirements —No interface glue logic required —Eliminates need for parallel to serial converters • Low Power CMOS —1.8V–3.6V, 2.5V–5.5V and 5V ±10% Versions —Standby Current Less than 1 µA —Active Current Less than 1mA • Byte or Page Write Capable —32-Byte Page Write Mode • Typical Nonvolatile Write Cycle Time: 2ms • High Reliability —100,000 Endurance Cycles —Guaranteed Data Retention: 100 Years DESCRIPTION The µPort Saver memories need no serial ports or spe- cial hardware and connect to the processor memory bus. Replacing bytewide data memory, the µPort Saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the µPort Saver provides all the serial benefits, such as low cost, low power, low volt- age, and small package size while releasing I/Os for more important uses. The µPort Saver memory outputs data within 25ns of an active read signal. This is less than the read access time of most hosts and provides “no-wait-state” operation. This prevents bottlenecks on the bus. With rates to 10 MHz, the µPort Saver supplies data faster than required by most host read cycle specifications. This eliminates the need for software NOPs. The µPort Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This “bit serial” interface allows the µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit systems. A Write Protect (WP) pin prevents inadvertent writes to the memory. Xicor EEPROMs are designed and tested for applica- tions requiring extended endurance. Inherent data reten- tion is greater than 100 years. BLOCK DIAGRAM CE I/O H.V. GENERATION TIMING & CONTROL EEPROM COMMAND DECODE AND CONTROL LOGIC X DEC Y DECODE DATA REGISTER WP 7008 FRM F02.1 OE WE ARRAY 16K x 8 P0/CS P1/CLK P2/DI P3/DO System Connection Internal Block Diagram µP µC Ports 8K x 8 2K x 8 Saved DSP ASIC A15 A0 D7 D0 OE WE MPS RISC X84161/641/129 AN95 • AN103 • AN107 |
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