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74ABT16821ADGG Datasheet(PDF) 8 Page - NXP Semiconductors |
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74ABT16821ADGG Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 8 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 8. Symbol Parameter Conditions 25 °C; V CC = 5.0 V −40 °C to +85 °C; VCC = 5.0 V ± 0.5 V Unit Min Typ Max Min Max fmax maximum frequency see Figure 5 160 250 - 160 - MHz tPLH LOW to HIGH propagation delay nCP to nQx, see Figure 5 1.3 2.4 3.3 1.3 3.7 ns tPHL HIGH to LOW propagation delay nCP to nQx, see Figure 5 1.1 2.0 2.6 1.1 3.0 ns tPZH OFF-state to HIGH propagation delay nOE to nQx; see Figure 6 1.4 2.5 3.3 1.4 4.1 ns tPZL OFF-state to LOW propagation delay nOE to nQx; see Figure 6 1.2 2.3 3.0 1.2 3.7 ns tPHZ HIGH to OFF-state propagation delay nOE to nQx; see Figure 6 1.6 3.2 4.1 1.6 4.8 ns tPLZ LOW to OFF-state propagation delay nOE to nQx; see Figure 6 1.3 2.3 3.1 1.3 3.3 ns tsu(H) set-up time HIGH nDx to nCP; see Figure 7 1.8 1.2 - 1.8 - ns tsu(L) set-up time LOW nDx to nCP; see Figure 7 +1.8 −0.9 - +1.8 - ns th(H) hold time HIGH nDx to nCP; see Figure 7 1.0 0.8 - 1.0 - ns th(L) hold time LOW nDx to nCP; see Figure 7 +1.0 −1.0 - +1.0 - ns tWH pulse width HIGH nCP; see Figure 5 2.5 0.8 - 2.5 - ns tWL pulse width LOW nCP; see Figure 5 2.5 1.0 - 2.5 - ns |
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