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74AHC2G32 Datasheet(PDF) 7 Page - NXP Semiconductors |
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74AHC2G32 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 13 page 74AHC_AHCT2G32_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 20 January 2009 7 of 13 NXP Semiconductors 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC2G32 VCC ≤ 3 ns 15 pF, 50 pF 1 k Ω open GND VCC 74AHCT2G32 3 V ≤ 3 ns 15 pF, 50 pF 1 k Ω open GND VCC |
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