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74AUP1G373 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G373 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 22 page 74AUP1G373_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 January 2008 3 of 22 NXP Semiconductors 74AUP1G373 Low-power D-type transparent latch; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition; X = Don’t care; Z = high-impedance OFF-state. Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP1G373 LE OE GND DQ 001aae250 1 2 3 6 VCC 5 4 74AUP1G373 GND 001aae251 LE D VCC OE Q Transparent top view 2 3 1 5 4 6 74AUP1G373 GND 001aae252 LE D VCC OE Q Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description LE 1 latch enable input (active HIGH) GND 2 ground (0 V) D 3 data input Q 4 latch output VCC 5 supply voltage OE 6 output enable input (active LOW) Table 4. Function table[1] Operating modes Input Internal latch Output OE LE D Q Enable and read register (transparent mode) LH LL L LH H H H Latch and read register L L l L L LLhH H Latch register and disable outputs H X X X Z |
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