74AUP1G386_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 2 July 2009

2 of 16

NXP Semiconductors

74AUP1G386

Low-power 3-input EXCLUSIVE-OR gate

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP1G386GW

−40 °C to +125 °C

SC-88

plastic surface-mounted package; 6 leads

SOT363

74AUP1G386GM

−40 °C to +125 °C

XSON6

plastic extremely thin small outline package; no leads;

6 terminals; body 1

× 1.45 × 0.5 mm

SOT886

74AUP1G386GF

−40 °C to +125 °C

XSON6

plastic extremely thin small outline package; no leads;

6 terminals; body 1

× 1 × 0.5 mm

SOT891

Table 2.

Marking

Type number

Marking code[1]

74AUP1G386GW

aH

74AUP1G386GM

aH

74AUP1G386GF

aH

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

mnb143

B

A

C

Y

6

3

1

4

1

6

= 1

4

mnb145

3

Fig 3.

Logic diagram

mnb144

A

B

C

Y