Electronic Components Datasheet Search |
|
74AUP2G32DC Datasheet(PDF) 10 Page - NXP Semiconductors |
|
74AUP2G32DC Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 17 page 74AUP2G32_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 8 January 2009 10 of 17 NXP Semiconductors 74AUP2G32 Low-power dual 2-input OR gate [1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, set-up and hold times and pulse width RL =1MΩ. Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k Ω or 1 MΩ open GND 2 × VCC |
Similar Part No. - 74AUP2G32DC |
|
Similar Description - 74AUP2G32DC |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |