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74AUP2G241DC Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP2G241DC Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 22 page 74AUP2G241_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 12 January 2009 3 of 22 NXP Semiconductors 74AUP2G241 Low-power dual buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8) 74AUP2G241 1OE VCC 1A 2OE 2Y 1Y GND 2A 001aaf437 1 2 3 4 6 5 8 7 74AUP2G241 1Y 2OE VCC 2A 2Y 1A 1OE GND 001aaf438 36 27 18 45 Transparent top view Fig 5. Pin configuration SOT996-2 (XSON8U) Fig 6. Pin configuration SOT902-1 (XQFN8U) 001aaj394 74AUP2G241 Transparent top view 8 7 6 5 1 2 3 4 1OE 1A 2Y GND VCC 2OE 1Y 2A 001aaf439 1A 1Y 1OE 2Y 2OE 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74AUP2G241 Table 3. Pin description Symbol Pin Description SOT765-1, SOT833-1 and SOT996-2 SOT902-1 1OE 1 7 output enable input 1OE (active LOW) 1A, 2A 2, 5 6, 3 data input 1Y, 2Y 6, 3 2, 5 data output GND 4 4 ground (0 V) 2OE 7 1 output enable input 2OE (active HIGH) VCC 8 8 supply voltage |
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