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bq24158YFFR Datasheet(PDF) 6 Page - Texas Instruments |
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bq24158YFFR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 40 page bq24153 bq24156, bq24158 SLUSA27 – MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BAD ADAPTOR DETECTION VIN(min) Input voltage lower limit BAD ADAPTOR DETECTION 3.6 3.8 4.0 V Deglitch time for VBUS rising above ms Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 VIN(min) Hysteresis for VIN(min) Input voltage rising 100 200 mV ISHORT Current source to GND During bad adaptor detection 20 30 40 mA tINT Detection Interval Input power source detection 2 S INPUT BASED DYNAMIC POWER MANAGEMENT Input Voltage DPM threshold programmable V VIN_DPM 4.2 4.76 range VIN DPM threshold accuracy –3% 1% INPUT CURRENT LIMITING TJ = 0°C – 125°C 88 93 98 mA IIN = 100 mA TJ = –40°C –125°C 86 93 98 IIN_LIMIT Input current limiting threshold TJ = 0°C – 125°C 450 475 500 mA IIN = 500 mA TJ = –40°C –125°C 440 475 500 VREF BIAS REGULATOR VBUS >VIN(min) or V(CSOUT) > V(BATMIN), V VREF Internal bias regulator voltage 2 6.5 I(VREF) = 1 mA, C(VREF) = 1 mF VREF output short current limit 30 mA BATTERY RECHARGE THRESHOLD V(RCH) Recharge threshold voltage Below V(OREG) 100 120 150 mV V(SCOUT) decreasing below threshold, Deglitch time 130 ms tFALL = 100 ns, 10-mV overdrive STAT OUTPUTS Low-level output saturation voltage, STAT IO = 10 mA, sink current 0.55 V pin VOL(STAT) High-level leakage current for STAT Voltage on STAT pin is 5 V 1 mA I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS VOL Output low threshold level IO = 10 mA, sink current 0.4 V VIL Input low threshold level V(pull-up) = 1.8 V, SDA and SCL 0.4 V VIH Input high threshold level V(pull-up) = 1.8 V, SDA and SCL 1.2 V I(BIAS) Input bias current V(pull-up) = 1.8 V, SDA and SCL 1 mA f(SCL) SCL clock frequency 3.4 MHz BATTERY DETECTION Battery detection current before charge Begins after termination detected, I(DETECT) –0.5 mA done (sink current) (1) VCSOUT ≤ V(OREG) tDETECT Battery detection time 262 ms SLEEP COMPARATOR Sleep-mode entry threshold, V(SLP) 2.3 V ≤ V(CSOUT) ≤ V(OREG), VBUS falling 0 40 100 mV VBUS – VCSOUT V(SLP_EXIT) Sleep-mode exit hysteresis 2.3 V ≤ V(CSOUT) ≤ V(OREG) 140 200 260 mV Deglitch time for VBUS rising above V(SLP) + Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 ms V(SLP_EXIT) UNDERVOLTAGE LOCKOUT (UVLO) VUVLO IC active threshold voltage VBUS rising - Exits UVLO 3.05 3.3 3.55 V VUVLO(HYS) IC active hysteresis VBUS falling below VUVLO - Enters UVLO 120 150 mV (1) Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low. 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24153 bq24156 bq24158 |
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