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74HC73D Datasheet(PDF) 4 Page - NXP Semiconductors |
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74HC73D Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 16 page 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 4 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 6. Functional description [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition; X = don’t care; ↓ = HIGH-to-LOW clock transition. 7. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. Table 3. Function table[1] Input Output Operating mode nR nCP nJ nK nQ nQ L X X X L H asynchronous reset H ↓ hh q q toggle H ↓ l h L H load 0 (reset) H ↓ h l H L load 1 (set) H ↓ llq q hold (no change) Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V IIK input clamping current VI < −0.5 V or VI >VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO >VCC + 0.5 V [1] - ±20 mA IO output current VO = −0.5 V to VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C DIP14 package [2] - 750 mW SO14 package [3] - 500 mW (T)SSOP14 package [4] - 500 mW |
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