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74LV132 Datasheet(PDF) 2 Page - NXP Semiconductors |
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74LV132 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 17 page 74LV132_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 2 July 2009 2 of 17 NXP Semiconductors 74LV132 Quad 2-input NAND Schmitt trigger 4. Ordering information 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV132N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74LV132D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV132DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LV132PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LV132BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) mna407 1A 1Y 1 3 1B 2 2A 2Y 4 6 2B 5 3A 3Y 9 8 3B 10 4A 4Y 12 11 4B 13 2 3 & 1 5 6 & 4 10 8 & 9 mna408 13 11 & 12 mna409 A Y B |
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